Analytic accounting for carrier velocity overshoot in advanced BJT´s for circuit simulation

An analytic model for electron velocity overshoot in advanced silicon-based bipolar junction transistors (BJTs) is presented. The model, which characterizes an effective saturated drift velocity in the collector space-charge regions, is intended for circuit simulation and has been implemented in MMSPICE. The model is based on a nonlocal augmented drift-velocity formalism that involves a length coefficient derived from Monte Carlo simulations. A phenomenological representation of the associated velocity relaxation is defined to be consistent with the overshoot analysis. Demonstrative MMSPICE device and circuit simulations show that effects of velocity overshoot in contemporary silicon BJTs produce only small performance enhancements, but can be exploited to optimize design tradeoffs in scaled technologies