Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology

Author

Gasiot, G. ; Giot, D. ; Roche, P.

Author_Institution

STMicroelectron., Crolles

Volume

53

Issue

6

fYear

2006

Firstpage

3479

Lastpage

3486

Abstract

Accelerated alpha-soft error rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 nm CMOS technology. Results are first compared to previous experimental radiation data in 130 nm and 90 nm. Second, the SER increase measured in 65 nm is investigated through (i) multiple cell upsets (MCU) counting and classification from experimental bitmap errors and (ii) full 3-D device simulations on SRAM bitcells to assess the PMOS-off sensitivity and the NMOS SEU threshold LET (LET_th) of each tested technologies. Finally, process changes are also scanned to shed light on the 65 nm SRAM response to alpha particles

Keywords

CMOS memory circuits; SRAM chips; alpha-particle effects; integrated circuit measurement; integrated circuit testing; life testing; radiation hardening (electronics); 3-D device simulations; 65 nm; CMOS technology; MCU counting; NMOS SEU threshold LET; PMOS-off sensitivity; SER; accelerated alpha-soft error rate measurements; experimental bitmap errors; multiple cell upsets; radiation-hardened SRAM; static random access memory; CMOS technology; Error analysis; MOS devices; Manufacturing; Neutrons; Performance evaluation; Radiation hardening; Random access memory; Single event upset; Testing; Alpha experiments; CMOS 65 nm; full 3-D device simulation; multiple cell upset; robust SRAM; soft error rate;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.885007

Filename

4033497