Single Event-Induced Error Propagation Through Nominally-off Transmission Gates

Author

Hutson, J.M. ; Ramachandran, V. ; Bhuva, B.L. ; Zhu, X. ; Schrimpf, R.D. ; Amusan, O.A. ; Massengill, L.M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN

Volume

53

Issue

6

fYear

2006

Firstpage

3558

Lastpage

3562

Abstract

A single event-induced false latching mechanism in 65-nm D-flip-flops is identified and attributed to transient propagation through nominally-off CMOS transmission gates. This is a circuit-level effect initialized by single event transient (SET) pulses that causes the hit node voltage to exceed the voltage supply rails. Smaller devices are more susceptible to this effect because of smaller nodal capacitances. Circuit simulations indicate that this effect increases the temporal window where a data bit is vulnerable to a node strike by a quarter clock cycle

Keywords

CMOS logic circuits; CMOS memory circuits; flip-flops; integrated circuit modelling; radiation hardening (electronics); 65 nm; D-flip-flops; circuit simulations; false latching mechanism; nominally-off CMOS transmission gates; quarter clock cycle; single event transient pulses; single event-induced error propagation; transient propagation; CMOS technology; Capacitance; Circuit simulation; Clocks; Combinational circuits; Failure analysis; Latches; Logic gates; Switches; Voltage; 65 nm technology; radiation effects; single event effects; transmission gate;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.885842

Filename

4033559