Title :
A Hardened-by-Design Technique for RF Digital Phase-Locked Loops
Author :
Loveless, T.D. ; Massengill, L.W. ; Bhuva, B.L. ; Holman, W.T. ; Witulski, A.F. ; Boulghassoul, Y.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN
Abstract :
A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. Furthermore, the design eliminates the charge pump as the most vulnerable module and significantly hardens the DPLL
Keywords :
digital phase locked loops; jitter; low-pass filters; power consumption; radiation hardening (electronics); DPLL single-event susceptibility; RF digital phase-locked loops; RF operation; RHBD topology; SET-resistant tri-state voltage-switching charge pump; analog single-event transients; circuit hardening by design; current-based charge pump; digital phase-locked loops; hardened-by-design technique; lock-in time; low-pass filter; phase jitter; power consumption; Charge pumps; Circuit simulation; Circuit topology; Clocks; Phase frequency detector; Phase locked loops; Radio frequency; Signal generators; Voltage; Voltage-controlled oscillators; Analog single-event transients; RF operation; charge pumps; circuit hardening by design; digital phase-locked loops;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2006.886203
