Title :
Optimization for SEU/SET Immunity on 0.15 μm Fully Depleted CMOS/SOI Digital Logic Devices
Author :
Makihara, A. ; Yamaguchi, T. ; Asai, H. ; Tsuchiya, Y. ; Amano, Y. ; Midorikawa, M. ; Shindou, H. ; Onoda, S. ; Hirao, T. ; Nakajima, Y. ; Takahashi, T. ; Ohnishi, K. ; Kuboyama, S.
Author_Institution :
High-Reliability Components Corp., Tsukuba
Abstract :
We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKI´s 0.15 mum Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/cm 2), demonstrating that the process was suitable for space applications with a little penalty
Keywords :
CMOS logic circuits; integrated circuit design; optimisation; radiation hardening; radiation hardening (electronics); silicon-on-insulator; 1.5 micron; LET; OKI; SET immunity; SET-free inverters; SEU-immune latches; commercial process; fully depleted CMOS/SOI digital logic devices; hardened logic cell design; hardness-by-design methodology; optimization; space applications; CMOS logic circuits; CMOS process; CMOS technology; Frequency; Immune system; Isolation technology; Logic devices; Signal generators; Single event upset; Space technology; Commercial process; SET; SEU; fully depleted CMOS/SOI; hardness-by-design;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2006.885166
