MOS Adaptive Memory Elements as Weights in an Adaptive Pattern Classifier

A solid-state adaptive memory element compatible with integrated network circuitry and a pattern classifier employing the unique adaption properties of this element are described. Each individual element consists of a resistor, a diode, and a special purpose MOS transistor all fabricated on a silicon substrate. Adaption in this case is accomplished by changing the electrical characteristics of the MOS transistor. This element is combined with a fixed reference resistor in a current-summing scheme to form a useful adaptive weight having both positive and negative values. The circuitry necessary for controlling the adaption of the element and its use as a weight during pattern classification is relatively simple and completely compatible with established integrated circuit technology. The pattern classifier can easily be trained to classify the majority of a given group of input patterns correctly according to arbitrarily selected "desired outputs."