Title :
Techniques and algorithms for fault grading of FPGA interconnect test configurations
Author :
Tahoori, Mehdi Baradaran ; Mitra, Subhasish
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
Conventional fault simulation techniques for field programmable gate arrays (FPGAs) are very complicated and time consuming. The alternative, FPGA fault emulation technique, is incomplete and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. The presented technique is able to report all detectable and undetectable faults and, compared with conventional methods, is orders of magnitude faster.
Keywords :
circuit simulation; fault simulation; field programmable gate arrays; integrated circuit testing; logic CAD; logic simulation; logic testing; FPGA chip; FPGA interconnects; configurable logic blocks; fault emulation; fault grading; fault model; fault simulation; field programmable gate arrays; test configurations; Circuit faults; Circuit testing; Computational modeling; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit testing; Logic testing; Manufacturing; Programmable logic arrays; Switches;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.822112
