Parasitics extraction with multipole refinement

Author

Beattie, Michael W. ; Pileggi, Lawrence T.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

23

Issue

2

fYear

2004

Firstpage

288

Lastpage

292

Abstract

Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today´s integrated systems, however, makes fast analysis crucial as well. We present a novel hierarchical potential evaluation technique which is able to represent detailed near-field and global far-field couplings with equal accuracy and efficiency by combining the best features of known hierarchical approaches in this field.

Keywords

capacitance; digital integrated circuits; inductance; integrated circuit interconnections; digital IC; global far-field couplings; hierarchical evaluation; inductive coupling; integrated circuits; interconnect modeling; interconnect parasitics; modern chip design; multipole refinement; near-field coupling; parasitic capacitance; parasitics extraction; Capacitance; Chip scale packaging; Conductors; Delay; Inductance; Logic; Performance analysis; Predictive models; Two dimensional displays; Wiring;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2003.822109

Filename

1262464