Title :
Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions
Author :
Sierawski, Brian D. ; Bhuva, Bharat L. ; Massengill, Lloyd W.
Author_Institution :
Inst. for Space & Defense Electron., Nashville, TN
Abstract :
The ever-decreasing charge required to represent a logic HIGH state at a circuit node has resulted in increased vulnerability of advanced ICs to Single-Event Upsets. Design approaches that address this threat to reliable operation of ICs are needed. The approach presented here uses logical masking through approximate functions to reduce the single-event error rate of a given circuit. Results on benchmark circuits show the effectiveness of this approach for mitigating the threat of SEU´s
Keywords :
error statistics; integrated circuit design; integrated logic circuits; masks; radiation effects; advanced IC; approximate logic functions; circuit node; integrated circuit radiation effects; logic HIGH state; logic circuits; logic design; logical masking; single-event upsets; soft error rate reduction; Clocks; Error analysis; Frequency; Logic circuits; Logic design; Logic functions; Pulse generation; Radiation effects; Single event upset; Voltage; Integrated circuit radiation effects; logic design; logical masking; single-event upsets; soft error rate;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2006.884352
