• DocumentCode
    871636
  • Title

    A statistical model for delay-fault testing

  • Author

    Park, E.S. ; Mercer, M.R. ; Williams, T.W.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • Volume
    6
  • Issue
    1
  • fYear
    1989
  • Firstpage
    45
  • Lastpage
    55
  • Abstract
    The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines the data for all delay faults to measure total delay-fault coverage. The authors also propose a model for measuring the defect level as a function of the manufacturing yield and the predictions of the statistical delay-fault coverage model.<>
  • Keywords
    logic testing; defect level; delay-fault testing; fault coverage; manufacturing yield; propagation delay; statistical model; system clock interval; Circuit faults; Circuit testing; Clocks; Delay effects; Logic; Predictive models; Propagation delay; Size measurement; System testing; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.20389
  • Filename
    20389