Title :
High-quality CMOS in thin (100 nm) silicon on sapphire
Author :
Garcia, G.A. ; Reedy, Ronald E. ; Burgener, M.L.
Author_Institution :
US Naval Ocean Syst. Center, San Diego, CA, USA
Abstract :
Electrical characteristics of enhancement-mode n-channel and p-channel MOSFETs in 100-nm-thick silicon-on-sapphire (SOS) are reported. Channel mobilities (linear operation) of 500 and 200 cm/sup 2//V-s, respectively, have been measured in double solid-phase epitaxially (DSPE) improved material. Deep trap levels associated with the Si-sapphire interface were measured in concentrations as low as 1*10/sup 11/ cm/sup -2/. These results indicate that DSPE-improved SOS films thinned to 100 nm are suitable for application to high-performance down-scaled CMOS circuitry.<>
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; semiconductor-insulator boundaries; 100 nm; SOS CMOS; Si-Al/sub 2/O/sub 3/; channel mobilities; deep trap levels; double solid phase epitaxy; down-scaled CMOS circuitry; enhancement mode MOSFETs; n-channel MOSFETs; p-channel MOSFETs; Annealing; Electric variables; Electrical resistance measurement; Fabrication; Implants; Sea measurements; Semiconductor films; Silicon; Solids; Substrates;
Journal_Title :
Electron Device Letters, IEEE
