RITUAL: a performance driven placement algorithm

An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints is described. The problem is formulated as a constrained programming problem and is solved in two phases: continuous and discrete. Constraints are placed on total path delays including cell and interconnect delays, and the behavior of all the paths is captured. Mathematical techniques and heuristics based on Lagrangian relaxation are used to find an approximate solution to the constrained problem. The algorithm yields good results, as shown on a set of real examples. On the average, between 8% and 30% improvement in the interconnect delay of these examples is obtained with little or no impact on chip area after routing by modifying the placement alone