A Patterning-Based Strain Engineering for Sub-22 nm Node FinFETs

We propose a strain engineering approach that is based on the patterning and under etching of fins using strained Si grown on SiGe strain relaxed buffers. The method enhances the strain of the patterned Fins up to ~ 2.9 GPa without the need of epitaxial source and drain stressors. We report a systematic simulation study on the scaling of this method for the present and future technology nodes down to 7 nm. Finally, we estimate that the technique deliveries an electron mobility enhancement up to 87% for FinFETs, independent of the technology node.