Improved systolic allpass digital filters for very high-speed applications

An improved systolic realisation of an arbitrary-order allpass digital filter for delayed N-path digital filtering is presented. Using this method, the sampling rate at the input and output of a delayed N-path digital filter can be reduced to (T_m+2T_a)/(N(N-1)) (where N>or=2, and T_m and T_a, respectively, represent the times for 2-input real multiplication and 2-input real addition), which is attractive for very high-speed applications.