Delay and Jitter Characterization for Software-Based Clock Synchronization Over WLAN Using PTP

In distributed systems, clock synchronization performance is hampered by delays and jitter accumulated not only in the network, but also in the timestamping procedures of the devices being synchronized. This is particularly critical in software timestamp-based synchronization where both software- and hardware-related sources contribute to this behavior. Usually, these synchronization impairments are collapsed into a black-box performance figure without quantifying the impact of each individual source, which obscures the picture and reduces the possibility to find optimized remedies. In this study, for the first time, the individual sources of delay and jitter are investigated for an IEEE 802.11 wireless local area network (WLAN) synchronization system using the IEEE 1588 protocol and software timestamps. Novel measurement techniques are proposed to quantify the hardware- and software-related delay and jitter mechanisms. It is shown that the delays and their associated jitter originate from both the WLAN chipset and the host computer. Moreover, the delay from the chipset cannot be considered symmetric and any such assumption inevitably leads to a residual offset, and thus to synchronization inaccuracy. Therefore, a calibration-based approach is proposed to compensate for these delays and to improve the performance of WLAN synchronization. Experimental results show that with optimal error compensation, a similar synchronization performance as software-based synchronization in Ethernet networks can be achieved.