Title :
Rise time optimization of high-speed digital fanout circuits
fDate :
6/1/1969 12:00:00 AM
Abstract :
Rise times of digital fanout circuits consisting of current-switched transistor pairs are analyzed. It is shown that minimum rise time can be obtained by a finite number of stages having approximately identical current gains. In the limiting case when the rise time originates solely from the gain-bandwidth product of the transistors, the optimum current gain per stage is e/SUP 1/2/=1.65.
Keywords :
Digital circuits; Optimisation; digital circuits; optimisation; Capacitance; Circuit analysis; Diodes; Electrical resistance measurement; Hafnium; Impedance; Linear accelerators; Time measurement; Transient analysis; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1969.1049978
