Title :
A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node
Author :
Yun, Jang-Gn ; Park, Il Han ; Cho, Seongjae ; Lee, Jung Hoon ; Kim, Doo-Hyun ; Lee, Gil Sung ; Kim, Yoon ; Lee, Jong Duk ; Park, Byung-Gook
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul
Abstract :
A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.
Keywords :
flash memories; random-access storage; 2-bit nonvolatile memory device; flash memory devices; lifted charge-trapping node; recessed channel structure; second bit effect; source-drain junction depth; 2-bit nonvolatile memory device; lifted charge-trapping node scheme; recessed channel structure; second bit effect (SBE);
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2008.2006049
