Title :
Hierarchical block boundary-element method (HBBEM): a fast field solver for 3-D capacitance extraction
Author :
Lu, Taotao ; Wang, Zeyi ; Yu, Wenjian
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for three-dimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.
Keywords :
Laplace equations; VLSI; boundary-elements methods; capacitance; circuit CAD; circuit complexity; integrated circuit design; integrated circuit interconnections; 3-D capacitance extraction; Laplace equation; boundary capacitance matrix; cross-bus structure; fast field solver; global capacitance matrix; global hierarchical approach; hierarchical block boundary-element method; hierarchical efficiency; hierarchical partition 3-D structure; interconnect capacitance; reuse technology; time complexity; very large scale integration; Acceleration; Conductors; Delay systems; Equations; Merging; Parameter extraction; Parasitic capacitance; Timing; Two dimensional displays; Very large scale integration;
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2003.821228