• DocumentCode
    874991
  • Title

    A new method for hierarchical compaction [VLSI]

  • Author

    Rülling, Wolfgang ; Schilz, Thomas

  • Author_Institution
    Fachhochschule Furtwangen, FB Ingenieur-Inf., Germany
  • Volume
    12
  • Issue
    2
  • fYear
    1993
  • fDate
    2/1/1993 12:00:00 AM
  • Firstpage
    353
  • Lastpage
    360
  • Abstract
    A framework for the compaction of hierarchically specified layout sketches is proposed. The main advantage of the method is that it maintains the layout hierarchy. Thus, the produced output has the same efficient representation as the input and further efficient processing of the layout becomes possible
  • Keywords
    VLSI; circuit layout CAD; integrated circuit technology; VLSI design; hierarchical compaction; layout hierarchy; Compaction; Minimization methods; Optimization methods; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.205014
  • Filename
    205014
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=874991