Title :
A clock power model to evaluate impact of architectural and technology optimizations - a summary
Author :
Duarte, David E. ; Vijaykrishnan, N. ; Irwin, Mary Jane
fDate :
6/25/1905 12:00:00 AM
Abstract :
The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock sub-system and the total system power budget is assessed.
Keywords :
SPICE; VLSI; clocks; digital phase locked loops; high level synthesis; microprocessor chips; parallel architectures; pipeline processing; reduced instruction set computing; SPICE simulations; VLIW machine; architectural optimizations; clock distribution circuitry; clock generation circuitry; clock power model; dynamic components; energy dissipation; high level model; high-level design; leakage power components; microprocessors power budget; network processor; phase-locked loop; pipeline registers clock load; superscalar RISC processor; synchronous digital systems; technology optimizations; Circuit simulation; Clocks; Design optimization; Digital systems; Energy dissipation; Microprocessors; Power generation; Power system modeling; SPICE; Synchronous generators;
Journal_Title :
Circuits and Systems Magazine, IEEE
DOI :
10.1109/MCAS.2003.1263398
