Abstract :
The present hardware, firmware, and software design and status of the Fastbus Micro-VAX, a two board Fastbus module packaging of the DEC Micro-VAX II computing system, will be described. The hardware currently features an Intel 80186, equipped with 64 kB of ROM, 32 kB of RAM, and an 82586/82501 Ethernet port, as a front end I/O processor, plus a high bandwidth Fastbus interface implemented in semi-custom ECL 100K VLSI with the Motorola MCA2500ECL macrocell array. Standard 80186 firmware implements multiple Fastbus segment drivers and interrupt receivers software compatible with the UPI, a limited Fastbus interprocessor network, and emulations of the DEC DEQNA Ethernet interface and an MSCP disk interface. Software includes device drivers for the non-DEC devices, plus appropriate standard access subroutines for the Fastbus and network devices. This work is supported by the U. S. Department of Energy under SBIR Contract DE-AC01-83ER80078.