• DocumentCode
    876365
  • Title

    ADC FASTBUS 12 Bits-96 Channels (ID : F6829)

  • Author

    Bellemain, A. ; Augé, E. ; Heusse, P.

  • Author_Institution
    Laboratoire de l´´Accélérateur Linéaire (IN2P3) Université de Paris-Sud, 91405-Orsay-France
  • Volume
    32
  • Issue
    4
  • fYear
    1985
  • Firstpage
    1339
  • Lastpage
    1340
  • Abstract
    The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 ¿s. Common analog threshold for zero suppression is available with possible choice of neighbours to be converted. The threshold action can be disabled by external input command (or CSR # 0 status). S.R. and broadcasts are implemented.
  • Keywords
    Broadcasting; Fastbus; Field programmable gate arrays; Hardware; Impedance matching; Latches; Logic testing; Multiplexing; Physics; Programmable logic arrays;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1985.4333606
  • Filename
    4333606
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=876365