Title :
ADC FASTBUS 12 Bits-96 Channels (ID : F6829)
Author :
Bellemain, A. ; Augé, E. ; Heusse, P.
Author_Institution :
Laboratoire de l´´Accélérateur Linéaire (IN2P3) Université de Paris-Sud, 91405-Orsay-France
Abstract :
The 96 input channels are multiplexed to six (12 bits) converters in such a way that adjacent channels are driven to different chips. The maximum conversion time is 65 ¿s. Common analog threshold for zero suppression is available with possible choice of neighbours to be converted. The threshold action can be disabled by external input command (or CSR # 0 status). S.R. and broadcasts are implemented.
Keywords :
Broadcasting; Fastbus; Field programmable gate arrays; Hardware; Impedance matching; Latches; Logic testing; Multiplexing; Physics; Programmable logic arrays;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1985.4333606
