Variation Aware Sleep Vector Selection in Dual ${\rm V}_{{{\rm t}}}$ Dynamic OR Circuits for Low Leakage Register File Design

Dual threshold voltage (Vt) technique is applied widely in dynamic OR circuits to achieve low leakage in register files (RF) design, but its effectiveness is significantly influenced by the selected sleep vector during the standby mode. As technology scales into deep nanometer era, the sleep vector selection in dual Vt dynamic OR (DV-OR) circuits becomes challenging due to the impact of PVT (process, supply voltage and temperature) variations. In this paper, we analyze the relationship among PVT variations, leakage characteristics, and sleep vectors in DV-OR circuits. We further perform a comprehensive study on sleep vector selection and explore its design space in DV-OR circuits. Finally, we present a generalization of our analysis for multiple Vt dynamic OR circuits and provide sleep vector selection guidelines to achieve low leakage and robust register files in modern processors.