A high-performance N-channel MOSLSI using depletion-type load elements

Author

Masuhara, Toshiaki ; Nagata, Minoru ; Hashimoto, Norikazu

Volume

7

Issue

3

fYear

1972

fDate

6/1/1972 12:00:00 AM

Firstpage

224

Lastpage

231

Abstract

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

Keywords

Integrated circuits; Invertors; Logic circuits; Monolithic integrated circuits; Read-only storage; Semiconductor storage devices; Semiconductor storage systems; Transistor-transistor logic; integrated circuits; invertors; logic circuits; monolithic integrated circuits; read-only storage; semiconductor storage devices; semiconductor storage systems; transistor-transistor logic; Capacitance; Circuit testing; Coupling circuits; Decoding; Integrated circuit noise; Inverters; Large scale integration; MOSFET circuits; Pulse circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1972.1050281

Filename

1050281