A MOST invertor with improved switching speed

A modified MOST invertor circuit consisting of a driver, load, and bias MOST is proposed. The gate voltage of the load MOST is supplied by the bias MOST. This leads to an improvement of both the output pulse height and the switching speed if the circuit is applied in dynamic logic. The switching transients are studied by considering first the dynamic loadlines of the driver and the load MOST, and second an analytical function has been developed predicting the 10-90 percent turnoff time of the circuit. The theoretical turn-off times are found to be in agreement with measurements on a breadboard circuit and from this a maximum gain in 10-90 percent turn-off time of the modified invertor of about a factor of 3, as compared with a conventional MOST invertor, appears to be attainable. The modified invertor circuit may also be used in static logic with conservation of its full advantages, provided that the minimum switching period is about 50 ns.