A novel saturation control in TTL circuits

A novel technique of saturation control in TTL and other saturated logic circuits is described and analyzed. The approach is not only fully compatible with standard bipolar transistor technology, but lends itself to integration. The device parameter tracking on a chip is utilized to suitably bias a feedback saturation control transistor so that the stored charge of a TTL gate output transistor is reduced by typically two orders of magnitude. Thus, the turn-off switching time is significantly decreased without noticeably affecting the turn-on delay time. The performance improvement is close to that achieved by the well-known Schottky diode clamp approach; however, the novel technique offers advantages in noise margin, control of down-level output voltage, and processing. The effectiveness of the proposed technique has been verified theoretically by computer circuit analysis and experimentally by bench setup measurements.