Title :
Atto-farad measurement and modeling of on-chip coupling capacitance
Author :
Arora, Narain D. ; Song, Li
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is discussed. The setup simply requires dc current measurement and the method has been tested for 180 nm and 130 nm technologies. Furthermore, the method can be easily implemented for on-wafer e-test measurement in a fab, to study die-to-die and wafer-to-wafer coupling capacitance variation due to manufacturing process variation. In one process, it has been observed that the coupling capacitance between parallel lines could vary as much as 17%.
Keywords :
VLSI; capacitance; electrical conductivity; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; VLSI chip; atto-farad measurement; atto-farad modeling; capacitance modeling; dc current measurement; die-to-die coupling capacitance; interconnect; on-chip coupling capacitance; on-wafer e-test measurement; very large scale integration; wafer-to-wafer coupling capacitance; Aluminum; Capacitance measurement; Copper; Current measurement; Dielectric materials; Integrated circuit interconnections; Parasitic capacitance; Semiconductor device measurement; Solid modeling; Very large scale integration;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.822651
