A voltage overscaled low-power digital filter IC

Author

Hegde, Rajamohana ; Shanbhag, Naresh R.

Author_Institution

Intersymbol Commun. Inc., Champaign, IL, USA

Volume

39

Issue

2

fYear

2004

Firstpage

388

Lastpage

391

Abstract

In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05f_s-0.25f_s, where f_s is the sampling frequency).

Keywords

CMOS digital integrated circuits; digital filters; error correction; low-power electronics; 0.35 micron; 3.3 V; CMOS technology; SNR; algorithmic noise tolerance; algorithmic performance degradation restoration; energy dissipation; energy efficiency; error-control; filter bandwidths; integrated circuit; optimally voltage-scaled systems; output signal-to-noise ratio; sampling frequency; supply voltage; voltage overscaled low-power digital filter IC; voltage overscaling; voltage scaling; CMOS digital integrated circuits; CMOS integrated circuits; CMOS process; Digital filters; Digital integrated circuits; Energy efficiency; Integrated circuit noise; Signal restoration; Throughput; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.821775

Filename

1263667