Title :
Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs
Author :
Giot, Damien ; Roche, Philippe ; Gasiot, Gilles ; Autran, Jean Luc ; Sørensen, Reno Harboe
Author_Institution :
Central CAD & Design Solution Group, STMicroelectronics, Crolles
Abstract :
Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets (MCUs) are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3-D TCAD simulations investigate the occurrence of parasitic bipolar effect.
Keywords :
SRAM chips; bipolar integrated circuits; integrated circuit design; integrated circuit testing; technology CAD (electronics); 3-D TCAD simulations; heavy ion testing; memory cell areas; multiple cell upset; parasitic bipolar effect; single-event upset; size 65 nm; size 90 nm; standard SRAM; CMOS process; CMOS technology; Error correction; Error correction codes; Manufacturing processes; Random access memory; Silicon; Single event upset; Space technology; Testing; 65 nm; Deep-Nwell; heavy ions; multiple-bit upset (MBU); multiple-cell upset (MCU); sensitive area; single-event upset (SEU); triple well (TW);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2008.916063
