Author :
Peyre, D. ; Poivey, Ch ; Binois, Ch ; Mangeret, R. ; Salvaterra, G. ; Beaumel, M. ; Pontoni, F. ; Bouchet, T. ; Pater, L. ; Bezerra, F. ; Ecoffet, R. ; Lorfèvre, E. ; Sturesson, F. ; Berger, G. ; Foy, J.C. ; Piquet, B.
Abstract :
This paper presents experimental data showing heavy ions inducing gate degradation in power MOSFETs. In the experiments, backside and front-side irradiations are performed. During backside irradiation, the heavy ion ranges are tuned in such way to control whether they hit the gate or not. Gate-to-source current Igss (Phi) is measured versus heavy ions (H.I.) fluence Phi. Post-irradiation-gate-stress-test (PGST) allows measurement of gate breakdown voltage VBD(Phi) which is observed to decrease with (H.I.) fluence. Based on these experimental results, a hypothesis of substrate-generated carriers impact overlap of multiple strikes may explain gate degradation until SEGR triggering. This last hypothesis is supported by a statistical model approach of heavy ions multiple impacts.
Keywords :
ion beam effects; power MOSFET; semiconductor device breakdown; backside irradiation; front-side irradiation; gate breakdown voltage; gate-source current; heavy ion; multiple impacts; power MOSFET; single-event gate rupture; Annealing; Current measurement; Degradation; Helium; MOSFETs; Microelectronics; Radiation effects; Radiation hardening; Synthetic aperture sonar; Testing; Cumulative phenomenon; heavy ions (H.I.); multiple impacts; post-irradiation-gate-stress-test (PGST); power MOSFET; single-event gate rupture (SEGR);
