DocumentCode :
877777
Title :
A study of failures identified during board level environmental stress testing
Author :
Parker, T. Paul ; Webb, Cathy W.
Author_Institution :
AT&T Little Rock, AR, USA
Volume :
15
Issue :
6
fYear :
1992
fDate :
12/1/1992 12:00:00 AM
Firstpage :
1086
Lastpage :
1092
Abstract :
AT&T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling (TC), random vibration, etc. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST
Keywords :
environmental testing; failure analysis; life testing; printed circuit testing; quality control; AT&T; EST; board level environmental stress testing; burn-in techniques; circuit board designs; customer first month failure rates; early life failures; environmental stress testing; functional monitoring; outgoing quality audits; random vibration; study of failures; temperature cycling; thermal cycling; thermal stressing; Application software; Assembly; Circuit testing; Failure analysis; Human factors; Life testing; Manufacturing processes; Production; Thermal stresses; Total quality management;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/33.206935
Filename :
206935
Link To Document :
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