Write-current control and self-powering in a low-power memory cell

A modification of a previously published dc-stable all-transistor memory cell is described that reduces the write current required for high speed writing. Moreover, it introduces a self-powering mechanism that improves the writing speed up to a factor of 10 at small cell standby currents in the order of 1 /spl mu/A. In addition cell area has been reduced by 40 percent to 9 mil/SUP 2/ by use of a shallower structure and tightened design rules.