DocumentCode
878123
Title
A dynamic delay line with a bipolar one-transistor cell
Author
Kasperkovitz, D.
Volume
8
Issue
4
fYear
1973
Firstpage
251
Lastpage
259
Abstract
A new bipolar one-transistor cell for the storage of analog information is described. This cell forms the basis of a 256-sample dynamic delay line, where 16/spl times/16 cells of a two-dimensional array are successively accessed. The circuitry for the generation of the selection voltages is specially designed in order to make the power dissipation independent of the size of the delay line.
Keywords
Analogue storage; Bipolar transistors; Delay lines; Random-access storage; Semiconductor storage devices; analogue storage; bipolar transistors; delay lines; random-access storage; semiconductor storage devices; Capacitance; Charge coupled devices; Charge transfer; Circuits; Delay effects; Delay lines; Power dissipation; Power generation; Voltage; Writing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1973.1050393
Filename
1050393
Link To Document