Subnanosecond emitter-coupled logic gate circuit using Isoplanar II

Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.