Title :
Suggestion for an i.c. fast parallel multiplier
Author_Institution :
Istituto Elettrotecnico Nazionale `Galileo Ferraris¿, Torino, Italy
Abstract :
A general method for handling partial products in a parallel multiplier is proposed. It leads to a network of AND gates and full adders, availables as i.c.s which can have an operation time of less than 10 ns per bit of the result.
Keywords :
digital arithmetic; digital integrated circuits; multiplying circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19690034
