DocumentCode
87867
Title
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform
Author
Agrawal, Pulin ; Milojevic, Dragomir ; Raghavan, Praveen ; Catthoor, Francky ; Van der Perre, Liesbet ; Beyne, Eric ; Varadarajan, Ravi
Author_Institution
IMEC, Leuven, Belgium
Volume
6
Issue
4
fYear
2014
fDate
Dec. 2014
Firstpage
85
Lastpage
88
Abstract
3D integration is being explored as a viable alternative to overcome limitations faced by mobile MPSoC platforms in traditional 2D designs. TSV based interdie connection is the most widely used approach currently. Although, TSV dimensions are scaling down, they still impose a restriction on the interdie connections density and the granularity at which 3D partitioning can be carried out. These limitations will aggravate in future scaled technologies. Alternatives such as Cu-Cu bonding need to be explored to achieve very fine-pitch and high density interdie connections. In this letter, we carry out a system architecture level comparison for a complex MPSoC platform instantiated for wireless PHY processing (WLAN and LTE). We compare 2D and 3D using: 1) TSVs with μ bump and RDL (F2B); and 2) Cu-Cu bonding (F2F). We show significant gains in 3D as compared to 2D. We also show that F2B and F2F have different system level architecture requirements, and that their impact on parameters at interconnect and system architecture level varies.
Keywords
mobile computing; system-on-chip; 3D integration technologies; 3D partitioning; LTE; WLAN; interdie connection; mobile MPSoC platform; system level comparison; wireless PHY processing; Computer architecture; Copper; Integrated circuit interconnections; Multiprocessing systems; Three-dimensional integrated circuits; Through-silicon vias; 3D stacked integrated circuits (3D-SIC); Cu-Cu bonding; MPSoC; interconnect; through-silicon via (TSV);
fLanguage
English
Journal_Title
Embedded Systems Letters, IEEE
Publisher
ieee
ISSN
1943-0663
Type
jour
DOI
10.1109/LES.2014.2360642
Filename
6911936
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