Architecture design of full HD JPEG XR encoder for digital photography applications

Author

Pan, Chia-Ho ; Chien, Ching-Yen ; Chao, Wei-Min ; Huang, Sheng-Chieh ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

Volume

54

Issue

3

fYear

2008

fDate

8/1/2008 12:00:00 AM

Firstpage

963

Lastpage

971

Abstract

To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 times 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features.

Keywords

VLSI; codecs; data compression; image coding; photography; HD JPEG XR encoder; VLSI architecture; digital photography; high definition photography; image compression; Digital cameras; Digital images; Digital photography; Discrete wavelet transforms; Displays; High definition video; IEC standards; ISO standards; Image coding; Transform coding; High Definition Photo; JPEG XR; Joint Photographic Experts Group (JPEG); VLSI Architecture;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2008.4637574

Filename

4637574