Optimization of the latching pulse for dynamic flip-flop sensors

Analysis of dynamic IGFET flip-flop charge sensors shows that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope. Latchup time is approximately inversely proportional to the initial voltage imbalance. Capacitive coupling between the two sides of the flip-flop generates a voltage excursion of the off-side even when there is no off-side conduction. With a 10-V latching ramp, the off-side is no off-side conduction. With a 10-V latching ramp, the off-side voltage excursion is typically about 2 V, and full latchup is attained in about 75 ns for an initial imbalance of 0.5 V. If a small off-side conduction is allowed, then latchup time can be reduced by a factor of two or more. The penalty is a few tenths of a volt added excursion of the off-side voltage. Computer circuit simulations were used to verify the analytic derivations.