Defect analysis and yield degradation of integrated circuits

Various attempts have been made to analyze the yield of integrated circuits in the presence of point defects. This paper analyzes the yield considering both radial and angular variation in the defect density. The effect of statistical variations in the average defect density from slice to slice is also included. Different types of defects which affect the yield are reviewed. The degradation in yield due to point defects, line defects, area defects, and defect clusters is considered in detail. A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions. The results are primarily applicable to large integrated circuit chips.