Title :
Single-event effects in 0.18 μm CMOS commercial processes
Author :
Makihara, A. ; Sakaide, Y. ; Tsuchiya, Y. ; Arimitsu, T. ; Asai, H. ; Iide, Y. ; Shindou, H. ; Kuboyama, S. ; Matsuda, S.
Author_Institution :
High-Reliability Components Corp., Ibaraki, Japan
Abstract :
We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 μm CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.
Keywords :
CMOS integrated circuits; radiation hardening (electronics); 0.18 μm CMOS commercial processes; 0.18 micron; SEEs; hardness-by-design methodology; single-event effects; CMOS process; Circuits; Epitaxial layers; Flip-flops; Foundries; Latches; Single event upset; Space technology; Substrates; Testing;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2003.821830
