DocumentCode
879749
Title
Predicting Signal Degeneration and Gate Compatibility in Logic Circuits
Author
Pierce, William H.
Author_Institution
Information Devices Research Department, Westinghouse Research and Development Center. Pittsburgh, Pa.
Issue
3
fYear
1963
fDate
6/1/1963 12:00:00 AM
Firstpage
277
Lastpage
281
Abstract
A simple graphical analysis of the output vs input curves of a digital circuit will show whether the circuit can be used in arbitrarily long logical chains. The analysis uses upper and lower bounds for the output vs input curves, but these bounds can be interpreted as statistical confidence limits. Results of the analysis give necessary and sufficient conditions for various different types of gates to be compatible.
Keywords
Circuit synthesis; Digital circuits; Logic circuits; Network synthesis; Probability distribution; Signal analysis; Signal generators; Signal synthesis; Temperature distribution; Voltage;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1963.263541
Filename
4037864
Link To Document