DocumentCode
879805
Title
A single event latchup suppression technique for COTS CMOS ICs
Author
Spratt, James P. ; Pickel, James C. ; Leadon, Roland E. ; Lacoe, Ronald C. ; Moss, Steven C. ; LaLumondiere, Stephen D.
Author_Institution
Full Circle Res. Inc., San Marcos, CA, USA
Volume
50
Issue
6
fYear
2003
Firstpage
2219
Lastpage
2224
Abstract
Results are presented on technique using displacement damage from energetic ions to suppress single event latchup in commercial off-the-shelf (COTS) CMOS integrated circuits. Ions implanted through the back of a thinned chip degrade the parasitic bipolar transistors causing latchup without degrading chip functionality or the parametrics of the chip.
Keywords
CMOS integrated circuits; bipolar integrated circuits; bipolar transistors; ion beam effects; radiation hardening (electronics); COTS CMOS ICs; commercial off-the-shelf integrated circuits; displacement damage; energetic ions; parasitic bipolar transistors; single event latchup suppression technique; suppress single event latchup; thinned chip; Bipolar transistors; CMOS integrated circuits; CMOS technology; Charge carrier lifetime; Costs; Degradation; Ion implantation; Manufacturing; Neutrons; Semiconductor device modeling;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2003.821607
Filename
1263863
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