Abstract :
The design and experimental investigation of a Josephson tunneling memory cell with nondestructive readout (NDRO) is described. The cell consists of a relatively large (20/spl times/25 mil/SUP 2/) superconductive loop which contains two Josephson tunneling write gates. NDRO is performed with a third gate per cell. It is shown that such a cell is an L, R, C parallel circuit which must be critically damped. Design equations are established which ensure critical damping solely with the single-particle tunneling resistance of the gates. Current transfer time (cell switching time) was measured to be /spl sime/600 ps. From two consecutive write cycles it was estimated that writing could be performed with a repetition rate of /spl ges/1 GHz. No loss in circulating current was detected after 5/spl times/10/SUP 8/ NDRO cycles. The operating margins, measured without word, bit, and sense disturbs, allowed independent variations of /spl plusmn/11.5 percent in word current, /spl plusmn/26 percent in bit current, and /spl plusmn/15 percent in sense current. These results show that ultra high speed random access NDRO memories with zero standby power can be built with Josephson devices. Smaller switching times are expected in miniaturized memory cells.
