A 20-MHz p-n-p-n shift register with current mirror coupling

An experimental 4-bit static two-phase shift register is described which uses p-n-p-n switches as bistable elements. A new current mirror coupling between these elements has two advantages. 1) The turnoff of the slow p-n-p-n switches occurs in two clock phases. This results in a high clock frequency of 20 MHz at low average power dissipation of 200 /spl mu/W/bit. 2) A very compact cell design is possible, resulting in a high bit density of 80 bit/mm/SUP 2/ with a standard bipolar process and conservative layout rules. The limiting values of the clock-pulse voltages are measured and discussed in qualitative terms.