Title :
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques
Author :
Park, Churoo Chul-Woo ; Chung, Hoeju ; Yun-Sang Lee ; Kim, Jaekwan ; Lee, Yun-Sang ; Chae, Moo-Sung ; Jung, Dae-Hee ; Choi, Sung-Ho ; Seo, Seung-Young ; Park, Taek-Seon ; Shin, Jun-Ho ; Cho, Jin-Hyung ; Lee, Seunghoon ; Song, Ki-Whan ; Kim, Kyu-hyoun ; Le
Author_Institution :
Samsung Electron. Co., Ltd, Gyeongi-Do, South Korea
fDate :
4/1/2006 12:00:00 AM
Abstract :
A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and CIO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.
Keywords :
DRAM chips; calibration; driver circuits; electrostatic discharge; 1.5 V; 512 Mbit; 80 nm; CIO minimization; DDR3 SDRAM prototype; DDR3 point-to-2points interfacing; DDR3 synchronous DRAM prototype; SCR type ESD protection; double data rate SDRAM; hybrid latency control scheme; on-chip sensor; on-die-termination; per-bank-refresh; self-calibration techniques; signal integrity; temperature read-out; Bandwidth; Calibration; Consumer electronics; Pipeline processing; Prefetching; Prototypes; Random access memory; SDRAM; Temperature sensors; Thyristors; Calibration; DDR3 SDRAM; SCR type ESD; input capacitance; per-bank refresh; signal integrity; temperature sensor;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.870808
