Title :
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC
Author :
Dai, Fa Foster ; Ni, Weining ; Yin, Shi ; Jaeger, Richard C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
fDate :
4/1/2006 12:00:00 AM
Abstract :
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage ΔΣ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q2 Random Walk switching scheme. The ΔΣ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage ΔΣ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-μm CMOS technology with active area of 1.11mm2 including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm2. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.
Keywords :
CMOS integrated circuits; delta-sigma modulation; direct digital synthesis; read-only storage; 0.35 micron; 12 bit; 16 bit; 200 mW; 3.3 V; 8 bit; CMOS technology; DDFS prototype; ROM size; current-steering DAC; delta-sigma noise shaper; direct digital frequency synthesizer; fourth-order phase domain noise shaper; phase truncation error; random walk switching scheme; single-stage delta-sigma interpolator; spurious-free dynamic range; CMOS technology; Finite wordlength effects; Frequency synthesizers; Noise reduction; Noise shaping; Phase measurement; Phase noise; Prototypes; Read only memory; Size measurement; CMOS integrated circuits; data conversion; delta-sigma modulation; digital-to-analog conversion; direct digital synthesizer; frequency synthesizers; integrated circuit design; sigma-delta modulation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.870749
