A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS

Author

Jaeha Kim ; Jeong-kyoum Kim ; Lee, Bong-Joon ; Namhoon Kim ; Jeong, Deog-Kyoon ; Kim, Namhoon

Author_Institution

Seoul Nat. Univ., South Korea

Volume

41

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

899

Lastpage

908

Abstract

A 20-GHz phase-locked loop with 4.9 ps_pp/0.65 ps_rms jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g_m oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-μm CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.

Keywords

CMOS integrated circuits; filters; frequency dividers; microstrip resonators; microwave oscillators; phase locked loops; phase noise; transmitters; 0.13 micron; 17.6 to 19.4 GHz; 20 GHz; 40 Gbit/s; 480 mW; CMOS process; design iteration procedure; microstrip resonator; phase noise; phase-locked loop; pulsed latches; sampled-feedforward loop filter; serializing transmitter; static frequency dividers; Frequency conversion; Inverters; Jitter; Oscillators; Phase locked loops; Phase noise; Resistors; Resonator filters; Switches; Transmitters; CMOS; VCO optimization; frequency divider; phase-locked loop (PLL); pulsed latch; reference spur;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.870766

Filename

1610635