Peripheral circuits for one-transistor cell MOS RAM´s

The use of a single transistor and storage capacitor allows MOS dynamic memories to be built with cell areas of less than two square mils. The logic signals then available are unusually small and balanced sensing is commonly used. Such sense amplifiers and other on-chip circuits peripheral to the memory array are increasingly important in determining the total area and cost, the performance and testing difficulties. This paper describes some of the key peripheral circuits used in a practical 4K random-access memory (RAM) design paying particular attention to these factors. A `margin test´ facility is designed into the form of sense amplifier used and allows measurement of cell storage levels and sense amplifier offset to ensure that adequate signal margins exist in the memory.