CMOS/SOS serial-parallel multiplier

A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil×170 mil chip. The operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand, a, to form the serial product. An addend, b, can also be accommodated to produce ax+b. The design of the multiplier cells are based on functional majority logic adders and weak or trickle inverter master-slave latches. The chip operates at clock rates up to 18 MHz. Power dissipation at 10 MHz and V/SUB DD/ of 5 V is about 20 mW, and the energy consumption for multiplying two 16-bit numbers is about 64 nJ. Typical application areas are mentioned.