• DocumentCode
    880753
  • Title

    A High-Speed Arithmetic Unit Using Tunnel Diodes

  • Author

    Daly, W.G. ; Kruy, J.F.

  • Author_Institution
    Honeywell-EDP Division, Needham, Mass.
  • Issue
    5
  • fYear
    1963
  • Firstpage
    503
  • Lastpage
    511
  • Abstract
    This paper describes a high-speed arithmetic unit which utilizes a ``sub-multiple algorithm´´ in both multiplication and division. The organization and circuits, which make the algorithm practical and economical, are presented. High performance in the unit is achieved by the use of tunnel diodes in four key areas, namely, in a tunnel diode memory using nondestructive readout, in the memory selection drivers, in a tunnel diode adder and in a bidirectional shift register. The unit performs a fixed point binary multiplication and division of two 44-bit operands in 2.75 ¿sec and 12 ¿sec, respectively. An experimental arithmetic unit has been built and operated in conjunction with a computer.1 Propagation delays of less than 2.2 nanoseconds were achieved between logic stages of a 48-bit binary full adder. Some results of the evaluation tests are also discussed.
  • Keywords
    Adders; Circuit testing; Costs; Digital arithmetic; Diodes; Driver circuits; Logic circuits; Performance gain; Registers; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electronic Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0367-7508
  • Type

    jour

  • DOI
    10.1109/PGEC.1963.263644
  • Filename
    4037964